Conventional semiconductor inspection devices were compatible with 100 mm design rules. However, samples of the object to be inspected are becoming diversified such as a wafer, exposure mask, EUV mask, NIL (nano imprint lithography) mask and substrate and presently devices and technology which are compatible with sample design rules of 5˜30 nm are being demanded. That is, devices and technology in which L/S (line space) or hp (half pitch) node are in the 5˜30 nm generation are being demanded. It is necessary to obtain a high resolution capability when inspecting such samples using an inspection device.
Here, a sample can be an exposure mask, an EUV mask, a nano print mask (and template) a semiconductor wafer, an optical element substrate, or optical circuit substrate etc. These are separated into those with patterns and those without patterns. Those that include patterns are further separated into those that have uneven structure and those that do not. A pattern that does not include uneven structure is formed using a different material. Those that do not include patterns are separated into those that are coated with an oxide film and those that are not coated with an oxide film.
Here, the problems associated with inspection devices having conventional technologies are summarized as follows.
The first problem is related to a deficiency in resolution and throughput. In the conventional technology of mapping optical systems pixel size was about 50 nm and aberration was about 200 nm. Further, it was necessary to reduce aberration, reduce the energy width of an irradiation current, reduce pixel size and increase the amount of current in order to improve high resolution capabilities and throughput.
Secondly, in an SEM type inspection, when objects having a fine structure are increasingly inspected the greater the problem of throughput becomes. This is because the image resolution is insufficient if a smaller pixel size is not used. These are the cause of a SEM mainly forming an image due to edge contrast and performing defect inspection. For example, an inspection requires 6 hr/cm2 at 5 nmPx size and 200 MPPS. This would require 20˜50 times the amount of time required for a mapping projection type which is unrealistic for an inspection. International Publication WO20002/001596, Japanese Laid Open Patent No. 2007-48686, and Japanese Laid Open Patent H11-132975 are referred to as conventional technology.